Comparative soft error evaluation of layout cells in FinFET technology

Keywords: Soft error Bulk FinFET MUSCA SEP3 VLSI design Supply voltage Soft error sensitivity a b s t r a c t This work presents a comparative soft error evaluation of logic gates in bulk FinFET technology from 65-down to 32-nm technology generations. Single Event Transients induced by radiations are modeled with the MUSCA SEP3 tool, which explicitly accounts for the layout and the electrical properties of transistors. Good agreement between the calculated transient current, and TCAD mixed-mode simulations is demonstrated. This work allows for estimating the SER of such logic gates for ground applications, as well as for understanding the impact of voltage and drive strength through analysis of the sensitivity to soft errors. In the last decade, the aggressive scaling of CMOS technology has posed formidable challenges in terms of electrostatic control of the channel, which is needed to sustain performance improvements and mitigate short-channel effects in down-scaled technology generations ; leakage suppression and reduction of sub-threshold slope, as needed to maintain the standby power within reasonable limits; random variations, which need to be kept within reasonable bounds to avoid excessive yield degradation and sustain energy/perfor-mance improvements [1–7]. FinFETs/multi-gate devices have been introduced in industrial manufacturing processes, among the available options of devices that can address the above challenges and maintain compatibility with CMOS process. As main benefits, FinFETs exhibit smaller process variations, higher current drive per unit width and lower leakage current, compared to the bulk counterpart [1–7]. Operation at finer technologies tends to degrade robustness in many respects [8], as the technology scaling below 65 nm has introduced new issues, such as multi-collection and high Soft Error (SE) sensitivity induced by energetic particles coming from space and terrestrial radiations. Recent work showed that FinFET technology has attractive properties that limit the increase in the occurrence of soft errors [9], as its 3D configuration exposes small SE-sensitive areas. From a design standpoint, the improvement of the reliability requires the accurate estimate of the SE susceptibility of FinFET standard cell libraries, in order to support the optimization of cells during the development of the library. This work presents a comparative Single Event Transient (SET) evaluation of logic gates for different layout styles in FinFET technology for different technologies. Because of lack of available experimental SE characterization of logic cells in FinFET technology, the simulation tool is an interesting alternative with the aim to anticipate the sensitivity trends. This …